In many applications in the semi-conductor industry (in a broad sense including both micro-electronics, micro-optics and micro-mechanics) it is often required to build components on both sides of a semiconductor wafer, such as a silicon wafer, for the manufacture of semi-conductor devices, such as sensors, micro-mirror arrays, just to mention a few.
In the prior art for packaging and interconnecting such devices wire-bonding has been the common technique. However, wire bonding is not cost-effective and for devices requiring many interconnection wires, such as array devices, it may not possible to attach wires at all. Therefore, over the last decade so called flip-chip mounting has been widely used for electronic components, to avoid the need of wire bonding, thereby allowing for simplification, improved quality and cost reduction in the back-end packaging/interconnection process. However, flip-chip bonding connects the device with “front-side” down. This is most often not possible for MEMS devices (MEMS=Micro-Electrical-Mechanical Systems), for example sensors and micro-mirrors, which need to have the front-side up.
Other techniques in this field have been based on the provision of metallized portions in holes extending through a wafer, for the purpose of establishing electrical contact between the two surfaces.
Such mixing of materials (i.e. metals and semiconductor material of the wafers) puts limitations on the subsequent processes that can be utilized for the manufacture of components, in terms of usable temperatures and chemical environments.
One method of the just mentioned kind is disclosed in U.S. Pat. No. 6,002,177.
A further method is disclosed in WIPO publication WO 01/65598 A1 (corresponding to published US patent application 2003/0022475 A1), by Vieux-Rochaz et al.
The method in the latter document comprises the provision of grooves on one side of a wafer, the grooves defining suitable closed patterns, e.g. rings, squares rectangles etc., filling the grooves with insulating material, building components matching the enclosed areas, making a plurality of second grooves from the bottom surface mating with the top grooves, filling said second grooves with insulating material, and building components on the bottom surface, using the thus formed electrical connections to connect the top and bottom components as desired.
This process is fairly complex, and the publication does not disclose the manufacture of a platform comprising electrical through connections (vias), and usable as a generally applicable starting substrate for semi-conductor applications.